Simple answer is that there’s still nothing comparable to M architecture. It has the benefit of unified memory and SoC which eliminates the bus. And being RISC, it has small fixed size instructions which can be read in batches, then any instructions that don’t have a dependency within the batch can be executed in parallel. This makes it possible to just add more cores and parallelize against them. You can’t do this with CISC because instructions are all different length, and figuring out the dependencies and what needs to be read into a batch becomes expensive really fast negating the gains of running stuff in parallel.
Simple answer is that there’s still nothing comparable to M architecture. It has the benefit of unified memory and SoC which eliminates the bus. And being RISC, it has small fixed size instructions which can be read in batches, then any instructions that don’t have a dependency within the batch can be executed in parallel. This makes it possible to just add more cores and parallelize against them. You can’t do this with CISC because instructions are all different length, and figuring out the dependencies and what needs to be read into a batch becomes expensive really fast negating the gains of running stuff in parallel.